1) Field of the Invention
The present invention relates to a technique for diagnosing/remedying a timing failure in an integrated circuit [for example, an LSI (Large Scale Integration)]. More specifically, the present invention relates to a technique for diagnosing/remedying a timing failure such as over-delay or the like occurring in an LSI having a plurality of same logic circuits [CPU (Central Processing Unit) cores].
2) Description of the Related Art
In order to determine whether an integrated circuit (for example, an LSI) is good or bad, as shown in FIG. 17, good/bad determination of an LSI 104 is carried out in the following manner, in general. In a scan chain 101 formed by connecting a plurality of flip-flops (denoted as “FF” in the drawing) 100-1 through 100-15 (hereinafter denoted simply by a reference character “100” when these flip-flops 100-1 through 100-15 are not specifically discriminated from one another) in series, setting values for the respective flip-flops are shifted in to be set in all the flip-flops, a clock is applied through a clock signal input circuit 102 and a clock delay adjusting circuit 103 thereto, and the values captured in the respective flip-flops are read out from the scan chain. It is then determined whether each of the values read out coincides with its expectation value.
Namely, after initial values are shifted from an SI (Scan In) input terminal 105 and set in respective flip-flops 100, a clock is applied, data passed through logic circuits (denoted as “Logic” in the drawing) 106-1 and 106-2 (hereinafter denoted simply by a reference character “106” when these logic circuits 106-1 and 106-2 are not specifically discriminated from one another) is thereby captured in the flip-flops 100-6 through 100-10, and 100-11 through 100-15 in the following stages.
For example, like the flip-flops 100-6 through 100-10 in the middle column (middle portion) in FIG. 17, the flip-flops 100 generally fulfill both functions of giving inputs to the logic circuit 106 and holding output values from the logic circuit 106 after a clock is applied.
The output values captured in the flip-flops 100 are shifted through the scan chain 101, read out from an SO (Scan Out) terminal 107 to the outside of the LSI 104, and compared with their expected values.
During the scan to read out the output values from the SO output terminal 107, data is simultaneously inputted to the SI terminal 105, whereby setting values for the next test can be given to the flip-flops 100.
In such known method, it is possible to detect which flip-flop 100 has a value differing from its expected value, that is, possible to specify a faulty flip-flop 100. Incidentally, over-delay can be detected by applying a plurality of clocks, and determining whether a time from update of a sending flip-flop 100 to update of a receiving flip-flop is within a predetermine period of time set beforehand.
In the case shown in FIG. 17, since it is possible to specify a faulty position (flip-flop 100) the failure may be solved by changing the setting value of the clock delay adjusting circuit 103 if the failure is a timing failure.
For this purpose, there is provided a mechanism in which the clock delay adjusting circuit 103 is provided to each clock distributing system, a clock delay setting value is set through a scan chain (clock delay setting information retaining unit) 108, and the delay is determined according to this signal.
When a timing failure is detected, the delay of a clock that drives a flip-flop 100 developing the timing failure may be adjusted.
There is another technique (refer to Patent Document 1 below, for example). According to this technique, the clock delay setting value retained in the scan chain 108 is changed to adjust the clock delay so that occurrence of the timing failure is decreased in a trial-and-error fashion, and a clock delay setting value at which the timing failure does not occur is finally searched, or a clock delay setting value at which the best performance is obtained is searched even though a relation between a position at which the timing failure occurs and the clock path to be adjusted is not specified.
In the recent LSI, the gate scale is very large, which causes an increase in number of flip-flips on the LSI. This leads to a longer scan shift time, which causes an increase in test time. This further causes problems with the test cost and TAT (Turn Around Time).
As a measure against these problems, there is logic BIST (Built In Self Test). In the logic BIST, flip-flops are set with known logic information such as outputs of a pseudo random circuit. Since the set values are generated inside the LSI, it becomes possible to increase the number of scan chains beyond the limitation of the number of LSI pins or a tester, thereby increasing the number of parallel scan chains to decrease each scan chain length, which allows a shorter test time.
If values captured in the flip-flops are all read out from the scan chains after a clock is applied, it means that the scan-in and the scan-out are performed concurrently. Thus, the effect of parallelization of the scan chains cannot be obtained. For this, the logic BIST outputs compressed data as its outputs.
In concrete, values of a number of paralleled scan chains are compressed into signatures by an MISR (Multiple Input Signature Register), and good or bad of the LSI is determined by whether the signatures agree or not.
In an LSI 109 shown in FIG. 18, for example, pseudo random numbers generated by an LFSR (Linear Feedback Shift Register) 110 are set as initial values in flip-flops 100 by scan shift.
Next, data passing through logic circuits 106 are captured into flip-flops 100-6 through 100-10 and flip-flops 100-11 through 100-15 when a clock is applied. The values in the flip-flops 100 are shifted through the scan chains, and signature values are calculated by an MISR 111. The signature values are retained in flip-flops (not shown) in the MISR 111, read out by a scan path 112 for read out only to the outside of the LSI 109, and compared with their expectation values.
The MISR 111 so calculates a signature value that the signature value differs from its expectation value at a considerably high rate (that is, a failure can be detected) when the output value of the logic circuit 106 is not correct, whereby the logic BIST can detect whether the LSI 109 operates normally or not.
In the logic BIST, it is possible to detect an over-delay failure by applying a plurality of clocks.
There is a technique that enables the timing test to be conducted at an actual operation speed of the LSI when the timing test is conducted on the LSI (for example, refer to Patent Document 2 below).
In the known logic BIST described above with reference to FIG. 18, a signature value compressed by the MISR 111 is compared with its expectation value. This provides only information about whether the LSI 109 operates normally or not, not providing information about a position at which the failure occurs, or the number of the failures. Namely, it is generally impossible to recon backward a flip-flop 100 (that is, a faulty flip-flop) that has retained the incorrect value on the basis of the signature value calculated by the MISR 111.
However, even in the known logic BIST, the timing failure may be solved by changing the clock delay value retained in the scan chain 108 or the cycle of the clock signal. In such case, the tested LSI 109 is diagnosed as that its logic circuit 106 is normal but a timing failure occurs therein.
Meanwhile, the logic BIST can detect a racing chip even when the chip has a logic failure due to open or short of the wiring or a timing failure.
In the LSI 109 diagnosed as that it has a normal logic but a timing failure occurs therein, the clock delay or the like has to be adjusted to solve the timing failure. However, the known logic BIST cannot detect a position of the timing failure, thus cannot guess at all which clock delay value needs to be changed to remedy the failure.
Since the known logic BIST cannot detect the number of timing failures, it is impossible to decrease the number of the failures in a trial-and-error fashion by changing the clock delay value or the like.
Further, when a position at which the failure occurs is unknown, it is impossible to conduct failure analysis, as well as the clock delay adjustment.
Accordingly, in the logic BIST in an LSI, particularly, an LSI having a plurality of processor cores (CPU cores) and a number of parallel scan chains, it is desirable to discriminate a position of the timing failure, the number of failures and so forth.
[Patent Document 1] Japanese Patent Application Laid-Open No. 2001-43261
[Patent Document 2] Japanese Patent Application Laid-Open No. 2003-4807